A memory-controlled crosspoint switch using E-beam restructuring

The design and yield analysis of a yield-enhanced crosspoint switch chip capable of operating at broadband rates is described. The chip, which is a prototype of a wafer-scale system, incorporates three levels of redundancy in order to increase the yield and the fault tolerance of the system. E-beam-programmable interconnect structures, using floating-gate FETs, implement customization and yield enhancement. A scanning-electron-beam lithography system is used to program these structures. An analysis of a wafer-scale crosspoint switch design extrapolated from the chip design indicates that an 80*75 array could be built with >90% yield.<
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