Error proof inkless die bonding process development

Wafer mapping techniques originated at the wafer fab for wafer manufacturing process control and yield improvement as presented by T. Takeda (1994). Recently, inkless assembly processes have been becoming more and more popular for wafer fab process simplification and cycle time reduction, as well as the graded IC product sale under the pressure of IC manufacturing cost. However, not all of the packaging and assembly houses are ready for wafer mapping, as converting from the current inked wafer process to inkless assembly includes a lot of challenges to assembly equipment, process and manufacturing control, especially for smaller die sizes (less than 1/spl times/1mm). This paper discusses the critical challenges of handling inkless wafers to packaging and assembly. Technical solutions are developed including error-proof inkless packaging process flow, reference die design, inkless die pick up arithmetic, and pattern recognition optimization. The scenarios of fatal impact to inkless wafer mapping implementation are captured and solutions are provided that guarantee smooth implementation of inkless assembly.