CMOS challenges of keeping up with Moore's Law

As the conventional scaling of CMOS technology is reaching its physical limitations, new materials and processes hold promise of giving CMOS a new lease on life. In order to turn an opportunity into a reality, the semiconductor industry is confronted with a daunting task of managing and co-integrating an unprecedented confluence of innovative approaches: high-k dielectric materials (HfO
₂
, HfSiON) possibly to be formed by atomic layer deposition (ALD) are needed to curb gate leakage current and thus power consumption; metal gates (TiN, TaC, MoN) are requisite for optimization of threshold voltages for MOSFETs allowing low voltage operation; engineered substrates (sSOI, SiGeOI, GOI, dual substrate orientation) along with uni-axial and biaxial stressor techniques are required to keep the channel carrier mobility high to effect further performance gains; higher-mass dopant species (B
₁₀
H
₁₄
) are being synthesized to enable ultra-shallow junction; new dopant activation techniques (spike, pulsed laser anneals) and new contact metallization (NiSi) are pursued to induce high dopant activation and low contact resistance, respectively. The introduction of these innovative approaches is coming at a high price, though: the new materials pose new set of concurrent, multifarious challenges both for unit process development and for process integration. This paper reviews the technology opportunities and focuses on the trade-offs between performance benefits, scalability, complexity, co-integrability (including prominently spatial and temporal constraints on thermal processing), and impact on metrology, yield, and reliability