Resist LER and LWR transfer during plasma etching processes for node 45 nm and beyond

As critical dimensions (CD) for semiconductor devices shrink to few tens of nanometers, the line edge roughness (LER) or line width roughness (LWR) becomes a critical issue because it can degrade resolution and linewidth accuracy (Yoshimura et al., 1993) and causes fluctuations of transistors performances (Croon et al., 2002). LER is currently calculated by performing "threshold" analysis. In this paper, we show the powerfulness of this technique which is able: first to characterize feature's profiles after the lithography step. Hence it enables to optimized parameters such as sidewall angle, CD and sidewall roughness. Then, we have fully characterized different plasma etching processes, which allow us to have access to parameters such CD bias, resist trimming rate, passivation layer thickness and shape measurement. At the end the CD-AFM enables us for example to have access to the CD-bias created on a global wafer by specific etching conditions and how the lithography LER is transferred during plasma etching processes.