Emerging alternative devices for CMOS and beyond

According to the latest version of the ITRS roadmap, CMOS scaling is predicted to continue into 2020 with physical gate lengths down to 5 nm. Driving forces are increased performance with smaller devices, increased functionality for larger chips and decreased cost per function. However to reach the predicted targets, large R&D efforts are required since both physical and technological limitations needs to be addressed. In this paper, an overview of the scaling issues is presented. The main limitations are leakage leading to excessive power consumption and short channel effects like threshold voltage (Vt) reduction, subthreshold swing (S) increase, drain induced barrier lowering (DIBL) and gate induced drain leakage (GIDL). Although lithography is for certain one of the most challenging issues, the research done in this area is beyond the scope of this presentation.