Scalable defect mapping and configuration of memory-based nanofabrics

Producing reliable nanosystems requires effectively addressing the high defect densities projected for nanotechnologies. Defect avoidance methodologies based on reconfiguration offer a promising solution to achieve defect tolerance. The idea is to start by obtaining a defect map of the target nanofabric, and then configure the desired functionality 'around' its defective components. In this paper, we argue for the suitability of memory-based computing nanofabrics, address the level of granularity at which defect mapping and configuration should be performed on such fabrics, and discuss the role of hierarchy towards controlling complexity. We then propose a group testing method to enable self-testing and self-configuration for appropriately architected memory-based nanofabrics. The proposed testing method is scalable and simple, in that it enables the entire fabric to be tested and configured using a relatively small number of easily configurable triple-module-redundancy (TMR) test tiles executing concurrently on different regions of the target nanofabric. Our experimental results demonstrate the effectiveness of the proposed method for a representative set of benchmark kernels.