A baseband transceiver architecture for WCDMA/HSDPA communications

In this paper, a baseband transceiver system, architecture design and verification for WCDMA/HSDPA communications is presented. The proposed receiver consists of a channel estimator for channel estimation and receiver parameter calculation, a carrier synchronization and timing synchronization block for carrier frequency offset and clock offset compensation, and an equalizer for ISI suppression. The receiver architecture design adopts applicable algorithms to design each building blocks but still with good performance or even better. The final simulation results show the proposed architecture can satisfy the system specification with better performance compared to other implementations.