A novel current-mode very low power analog CMOS four quadrant multiplier

In this paper, a novel current mode CMOS four-quadrant analog multiplier circuit is presented. The multiplication is implemented by four translinear loops with MOS transistors operating in weak inversion. Information carrying signals are differential balanced currents. The multiplier circuit has been implemented in a test chip in a standard 0.35 /spl mu/m CMOS technology. The experimental measurements (dc bias current of 250 nA and a power supply of 2.0 V) show a bandwidth of 200 kHz and a THD figure value lower than 0.9 %. The multiplier features a wide signal dynamic range and linearity, low power consumption (the maximum power consumption is of 5.5/spl middot/10/sup -6/ W) and very low area (18.7 /spl middot/10/sup -3/ mm/sup 2/). The multiplier is suitable for a wide range of analog signal processing applications. Due to the low power and silicon area consumption, scalability and modularity can be also easily integrated in massive parallel systems.