A high-speed capacitance extraction algorithm for multi-level VLSI interconnects

The authors present preliminary results of a novel stochastic algorithm for high-speed capacitance extraction in multi-level VLSI interconnects. The algorithm is related to a statistical procedure for solving Laplace's equation known as a floating random-walk method. Benchmark calculations for three-dimensional cross-wire geometries were performed on a MAC IIfx personal computer, operating at 0.3 MFLOPS. Execution times were typically 40 s for an accuracy of less that 5%. Overall computational efficiency stems from various factors: suitability to rectilinear geometries, statistical-error cancellation, selective integration over Gaussian surfaces, and direct capacitance-matrix evaluation.<
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