Technology and design challenges for mobile communication and computing products

Between 1970 and 2005, MOS feature size shrunk by 70/spl times/, transistor density increased by 5000/spl times/ and transistors per chip increased by 200,000/spl times/. The question is often asked whether such scaling will continue, and, if so, for how long. There is general consensus in the industry that Moore's Law scaling will continue for another 6 generations beyond 90 nm to 10 nm in the latter part of the next decade. But the scaling will require increasingly innovative solutions to the many challenging problems. This talk discusses the grand challenges of continued Moore's Law scaling for low power mobile communication and computing products: failure of gate insulator capacitance to scale with feature size; increase in power: static leakage power and active power; increase in variation of transistor and interconnect parameters, requiring increased design margin; performance degradation due to interconnect capacitance & resistance; embedded, low power memory and SOC integration of analog and RF functions.