Reconfiguring processor arrays using multiple-track models

The authors study a 3-track-1-spare model that has three tracks along each channel and one spare row or column along each boundary. It is shown that the model uses the spare processors very efficiently; specifically, it is proved that a 3-track-1-spare model can support any set of nonintersecting compensation paths. This provides theoretical justification of the observations made in the literature about the power of 3-track models. The authors also discuss efficient algorithms for reconfiguration in the 3-track-1-spare model and show that it has much higher reconfiguration probability than the corresponding 2 1/2-track-2-spare model.<
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