An automated electrical defect identification and location method for CMOS processes using a specially designed test chip

A test chip (named Yieldchip) was designed, simulated, fabricated, and tested on a 3- mu m process. The layout of the Yieldchip's cells enables the test program to electrically locate and identify active faults, thereby automating the, classification of defects. The Yieldchip can detect more than one defect per circuit in most circumstances. The algorithm can identify the 21 simple defects of the cells and can be used as an expert system to extend this list. Unidentified detectable faults are flagged at all times and located if possible.<
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