Materials limitations of amorphous-Si:H transistors

Application of two-terminal (back-to-back diode) and three-terminal (FET) amorphous-Si:H devices to the matrix addressing of liquid-crystal displays (LCD) is discussed. a-Si:H back-to-back diodes appear to be suitable switching elements for displays of intermediate complexity. These devices are easy to fabricate and appear to have a high yield. A n analysis of matrix-addressed LCD's shows that FET's implemented in a low-mobility material, such as a-Si:H, are best suited for (medium) high-resolution capacitorless displays where competing technologies (CdSe, poly-Si) are likely to encounter difficulties in meeting the off requirements. Instabilities in a-Si:H-based devices were studied by fabricating inverted and noninverted FET's with a variety of gate dielectrics: SiO
2
, both thermally grown and sputtered; Si
3
N
4
, both by GD and LPCVD; and evaporated SiO
x
. Comparison of these devices, which are listed in decreasing order of stability, showed that a-Si:H FET's with thermal oxide were stable. In other devices, the decrease of the source-drain current I
SD
with time was mainly caused by trapping at the semiconductor-dielectric interface. Feasibility of a-Si:H FET-addressed LCD's was studied by fabricating experimental 26 × 26 G-H LCD's by photolithographic methods on soda-lime glass substrates, using either GD Si
3
N
4
or sputtered SiO
2
as a gate dielectric. FET's use a ring layout for the gate geometry to maximize the off resistance and a positive photoconductivity-feedback mechanism to maximize the on current and to minimize cumulative trapping. The Schottky contact inverted FET's (
L = 25
µm;
W = 3800
µm) have a switching range > 10
⁶
. In dc conditions, at a source-drain voltage
V_{SD} = 10
V, the drain current I
SD
is typical < 1 pA at a gate voltage
V_{G} = 0
and > 1 µA at
V_{G} = 10
V. The transistor characteristics are time dependent. The channel mobility, as derived from the linear (triode) regime is about µ
eff
= 0'02 cm
²
/V . s at quasi-dc and increases with decreasing pulse length until it saturates at µ
eff
= 0.2 cm
²
/V . s. I
SD
decreases with time to about
\frac{1}{2}
to
\frac{1}{3}
of its initial value in ambient light (operating devices) and to about
\frac{1}{10}
in the dark, mostly due to trapping in the gate dielectric. The time-dependent decrease in I
SD
has been studied under dc conditions for the plasma-deposited SiO
2
and Si
3
N
4
gate insulators and under pulse conditions for Si
3
N
4
. Auger depth-profile analysis shows that the properties of amorphous hydrogenated silicon FET's are not very sensitive to the incorporation of common residual gases (O
2
, N
2
). Lifetime tests at room temperature and at 80°C for > 1 year have been carried out and the displays appear to be stable.