Avalanche-tunnel injection in MNOS transistor

Features and mechanism of the combination of hot electron injection and direct tunneling injection in p-channel MNOS memory transistors have been studied. It is made clear that injection near reversely biased source and drain junctions is hot electron injection, whereas injection in the middle of the channel region is mostly by direct tunneling, because the potential at the surface approaches that of source and drain due to the current flow distribution during avalanching. A two-dimensional Poisson's equation has been solved to quantitatively describe the avalanche-tunneling and compared with experimental results. The features of the avalanche-tunneling are in the single polarity writing for both "1" and "0" logic levels, which make it possible to implement EAROM and nonvolatile RAM without substrate isolation between the cell and the periphery.