A 4096-bit word-alterable ROM

The organization and operation of a 4096-bit MNOS word-alterable ROM is described. The device is primarily intended for ROM program storage with electrically alterable capability. However, it can also be used for slow-speed RAM applications where the number of erase-write cycles does not exceed 10
⁵
per word. Margining means are provided which can predict the device remanence for various erase and write times and reading conditions.