An architectural level test generator for a hierarchical design environment

Most state-of-the-art automatic test pattern generators (ATPGs) require a detailed gate level representation for the circuits under test, information that either does not exist or may not be available to the test engineers in a hierarchical design environment. An ATPG methodology working at an architectural level is proposed to exploit the hierarchy of the design and relieve the dependence on the gate level information. The test set for each high level primitive is pregenerated by any low-level sequential ATPG tool, based on any possible fault model. The test patterns in these test sets are justified and the fault effects are propagated at high level. Due to the fault collapsing effect, several data types have been defined for the manipulation of all possible fault effects. When conflict occurs and the backtracking mechanism is invoked, a novel tracing technique and an indexed backtracking technique are used to make high-level decisions.<
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