Design of address generation unit for audio DSP

The paper presents an address generation unit (AGU) for an audio DSP. The proposed AGU employs an enhanced FFT address generation unit (FAGU) that automatically calculates the butterfly input/output data addresses. The FFT is one of the key tasks for the modified discrete cosine transform (MDCT) mostly used in various audio algorithms. The number of FFT computation cycles can be reduced by the proposed FAGU. The proposed AGU has been synthesized using the SEC 0.18 /spl mu/m standard cell library. The proposed FAGU has been implemented and the gate count is 1,523. The size is decreased about 73% compared with the FAGU that we have previously proposed.