High-sensitivity InP/InGaAs DHBT decision circuit-design and application in optical and system experiments at 40-43 Gbit/s

A high-input-sensitivity decision D flip-flop integrated circuit was designed and fabricated in a self-aligned InP double heterojunction bipolar transistor technology (F/sub t/=180 GHz, F/sub max/=220 GHz). Circuit measurements at 40 Gbit/s show excellent eye quality, 15-mV sensitivity, and good clock phase margin. Two optical experiments, i.e., assessment of decision circuit reamplifying, reshaping, and retiming capabilities in 40-Gbit/s nonreturn-to-zero (full rate) photoreceiver and 43-Gbit/s optical signal noise ratio measurement (21.8 dB/0.1 nm for 10/sup -9/ BER) are also presented.