A low-parasitic collector construction for high-speed SiGe:C HBTs

We present a new collector construction for high-speed SiGe:C HBTs that substantially reduces the parasitic base-collector capacitance by selectively underetching of the collector region. The impact of the collector module on RF performance is demonstrated in separate bipolar processes for npn and pnp devices. A minimum gate delay of 3.2ps was achieved for CML ring oscillators with npn transistors featuring f/sub T//f/sub max/ values of 300GHz/250GHz at BV/sub CEO/ = 1.8V. For pnp devices with f/sub T//f/sub max/ values of 135GHz/140GHz at BV/sub CEO/ = 2.5V a gate delay of 5.9ps is demonstrated. Further vertical scaling of the doping profiles increases f/sub T/ to 380GHz at BV/sub CEO/=1.5V for npn's and 155GHz at BV/sub CEO/ = 2.3V for pnp's, but ring oscillator speed and f/sub max/ degraded.