A fast multiplier design using signed-digit numbers and 3-valued logic

A multiplier design using 3-valued (ternary) logic and redundant binary signed-digit (RBSD) numbers is presented. The use of 3-valued logic offers the advantage of reduced circuit complexity in terms of both transistor count and interconnections since each ternary bit can support one digit of the RBSD number system. The choice of a RBSD number system enhances the speed of multiplication by allowing carry-free addition of partial products. While the internal multiplication uses RBSD numbers, both the input operands and the output product are assumed to be in the standard two's complement form. MAGIC and SPICE software tools were used to produce VLSI design layouts and circuit simulation results.<
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