Modeling unbuffered latches for timing analysis

Unbuffered latches are often used in high-performance designs with custom timing flows. Adding these circuits to a standard library enables improved designs without blowing the library size. We observe a high potential frequency gain (up to 16%) for smaller power consumption. Accurate models for static timing analysis are required to reach a good point on the safety to performance trade-off. We are proposing a complete modeling methodology that can fit in a standard timing analysis flow. An accurate n-model is presented for the input impedance of an unbuffered latch with less than 2% error. We also present a new setup criteria required for these latches. We also show that more advanced waveform models are required to model the output. A Weibull waveform model proves to be effective in this case.