Simulation of interface roughness in DGMOSFETs using non-equilibrium Green's functions

In the sub-50 nm scale, the aggressive scaling of MOSFETs is expected to culminate in dual-gate (DG) architectures on SOI substrates. DGMOSFETs are widely accepted to be the ultimate design that silicon can deliver in terms of on and off currents (B. Yu, JEDM Tech. Dig. p. 937, 2001; K. Kim and J. Fossum, IEEE Trans. Elec. Dev., p. 2861, 2001). So far, the design efforts on these novel structures have concentrated on ideal geometries and doping profiles. However, at nanometer scale, current fabrication techniques cannot deliver perfect reproductions of the ideal design and suffer significantly from fluctuation effects associated with random doping and interfaces. It has thus become clear that accurate models for DGMOSFETs must account for interfaces beyond a planar division. In this work, we employ a modified nanoMOS simulator based on the non-equilibrium Green's function (NEGF) to model DGMOSFETs with rough interfaces.