An embedded DRAM for MDLNS FIR filter

This paper presents an embedded DRAM architecture that was developed specifically for programmable MDLNS FIR filter. A picture of the DRAM module as a complex entity is provided along with detailed operation analysis. The DRAM storage capacitor is formed with diffusion junction capacitance instead of trenched capacitor cell used by the conventional embedded DRAM, allowing seamless integration into logic part of entire design. Half voltage bitline precharge is accomplished by charge-sharing between true bitline and its complement bitline, resulting in minimum power consumption and low hardware complexity with no additional power source required. Simulation of a 64/spl times/20-bit DRAM in TSMC 0.18-/spl mu/m technology is provided, along with comparison to the conventional DRAM architectures.