Prototyping a hierarchical ring interconnect for system-on-chip multiprocessor implementations

This paper describes the prototype implementation of a hierarchical ring interconnect in programmable logic. Hierarchical rings provide advantages such as simplicity and modularity for system-on-chip implementation. Results are provided that demonstrate the operation of the hierarchical ring in hardware. Integration of the hierarchical ring with instances of a system-on-chip multiprocessor is discussed for supporting inter-processor communication either directly with special instructions or indirectly through memory.