A high resolution, wide range digital impedance controller for high-speed SRAM interface

This paper describes a digital impedance controller (DIC) for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23/spl Omega/ to 140/spl Omega/ with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is +2.26% with RQ ranging from 23/spl Omega/ to 53/spl Omega/ the same range covered by conventional scheme. High-resolution and wide range impedance control are implemented by using automatic gate voltage optimization. The data input valid window is 623ps at 0.75/spl plusmn/200mV and maximum eye open is 641mV meaning about 10% improvement at 1.5Gbps/pin DDR3 SRAM interface.