Design and implementation of RS(255,223) decoder on FPGA

This paper proposes a RS(255,223) decoder for applications that require high-speed data communication and reliability. The proposed architecture employs a modified Euclidean algorithm, the Chien search and Forney's algorithm using parallel processing technology. The complexity of this decoder is about 130,000 gates; the total latency is 560 cycles; and the throughput is 180Mbps under 20MHz. Comparing with similar designs, this design has smaller latency, moderate area, and high throughput rate.