Sensitivity analysis for on-chip /spl Delta/I-noise simulation

Power integrity gets increasing attention in the design of electronic packaging. Part of this discussion is the on-chip /spl Delta/I-noise. This paper presents a sensitivity analysis for high-frequency on-chip power noise distribution. The results help to optimize the effort required to achieve the needed accuracy of simulation. A generic description of the on-chip /spl Delta/I-noise simulation methodology is shown. In particular, the required input data is described. A sensitivity analysis has been performed to quantify the impact of each simulation parameter on the results. The nominal value of each input parameter has been varied in a range from 0.5/spl times/ to 2.0/spl times/ compared to a nominal case. The maximum /spl Delta/I-noise is plotted depending on the input parameter. The comparison to the nominal case shows which of the parameters have a high, medium or low impact on the simulated /spl Delta/I-noise. This paper shows which input parameter need to be accurate in order to obtain accurate simulation results.