Stacked-chip packaging: electrical, mechanical, and thermal challenges

A stacked-chip package offers many benefits, including improved electrical performance (shorter chip-to-chip interconnects), reduced printed circuit board (PCB) area, reduced weight, reduced cost when compared to a multi-package solution, and efficient integration of dissimilar integrated circuit (IC) technologies. The trade-offs to these improvements are the complex electrical, mechanical, and thermal challenges associated with stacked-chip packaging. These challenges put new demands on modeling and analysis capabilities. This paper describes these challenges and how modeling and simulation are used during package design to overcome them while improving overall module performance and reducing the qualification time and overall time to market.