PSS: a novel statement scheduling mechanism for a high-performance SoC architecture

Continuous improvements in semiconductor fabrication density are supporting new classes of system-on-a-chip (SoC) architectures that combine extensive processing logic/processor with high-density memory. Such architectures are generally called processor-in-memory (PIM) or intelligent memory (I-RAM) and can support high-performance computing by reducing the performance gap between the processor and the memory. The PIM architecture combines various processors in a single system. These processors are characterized by their computation and memory-access capabilities. Therefore, a strategy must be developed to identify their capabilities and dispatch the most appropriate jobs to them in order to exploit them fully. Accordingly, this study presents a new automatic source-to-source parallelizing system, called SAGE, to exploit the advantages of PIM architectures. Unlike conventional iteration-based parallelizing systems, SAGE adopts statement-based analyzing approaches. It adopts a new pair-selection scheduling (PSS) mechanism to achieve better utilization and workload balance between the host and memory processors of PIM architectures. This paper also provides performance results and comparison of several benchmarks to demonstrate the capability of this new scheduling algorithm.