Leakage current-based testing of CMOS ICs

As semiconductor technology advances, testing integrated circuits (ICs) has become a challenging task. Semiconductor manufacturers use various methods, including the functional test, the structural test and the speed or delay test. One of the most popular test methods is the leakage current, or I/sub DDQ/, test. The article describes the advantages of I/sub DDQ/ tests. As transistor geometries are scaled further, I/sub DDQ/ values and variations are projected to increase. Thus, we need to understand the components of the variation in I/sub DDQ/ to develop the most suitable screening method. I/sub DDQ/ tests will continue to remain an important and integral component of a test suite. However, I/sub DDQ/ measurements will need to be supported by rigorous statistical data analysis to reduce yield loss in the future. Manufacturers must he able to define their own statistical procedures to tune pass/fail criteria optimally. It may not be possible to bin the chips until the data from a lot of wafers are collected. The trends in lot-to-lot or wafer-to-wafer variations in I/sub DDQ/ must be monitored and used in the analysis procedures.