Experimental investigation of bare silicon wafer warp

IC packaging trends demand smaller packaging, which translates to thinner silicon; in some cases as thin as 50um. Thinning below 305um induces significant warp in product/metal wafers, which continues to increases as wafers are thinned further. Increased wafer warp results in handling/processing issues. Studies have been performed on product/metal wafers to characterize warp. These studies have shown a linear relationship between wafer warp and 1/thickness^2. Several factors, in combination, have been shown to contribute to warp in product/metal wafers such as: metal layers, polyimide layers, BCB layers, metal density, thermal stress, tilt direction, front side tension, backside tension, and gravity. The wafer warp phenomenon observed in product/metal wafers is also observed in bare silicon wafers. The difference between bare silicon test wafers and product wafers is the layering of the circuitry side on product/metal wafers, which has shown to be a large contributor to wafer warp. Damage to the wafer backside during conventional grinding can induce a large amount of warp in both product/metal and bare silicon wafers.