Use of experience plans optimisation method to design CMOS low noise amplifier for UMTS application

This paper presents the design of a CMOS low noise amplifier (LNA) suited for UMTS wireless standard. This standard of third wireless generation aims to focus on the already existing process in order to develop and improve actual service systems capacitance, like cordless and satellite systems. This objective can be obtained by improving system gain, increasing transmission data rate, etc. The designed amplifier uses differential structure, to ensure linearity and low noise figure. The noise model in this circuit is well mastered, however non linearity phenomenon is still very hard to encounter. For this reason, heuristics methods couldn't be applied to make transistors and passive element's sizing. In order to obtain a trade between linearity and noise figure, we propose here to use an optimization method based on experience plans. We designed an LNA with AMS 0.35/spl mu/m CMOS process. It provides a 19 dB gain at 2.14 GHz timing frequency and 2.4 dB noise figure (NF). The power consumption is 90 mW at 2.5 V power supply voltage. Simulation results are compared with the theoretical prediction and have shown the efficiency of our design methodology.