A 2GHz programmable counter with new re-loadable D flip-flop

A high-speed programmable counter with a new re-loadable D Flip-flop which integrates the programmable function to a single true-single-phase-clock (TSPC) D flip-flop is presented. The proposed re-loadable D flip-flop is able to operate at higher frequencies with lower power consumption in comparison to the performance of the existing bitcell. A programmable divide-by-N counter implemented with this re-loadable D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 2 GHz for a 1.8 V supply voltage with 4.7 mW power consumption.