Robust porous MSQ (k=2.3, e=12 GPa) for low-temperature (<350/spl deg/C) Cu/low-k integration using ArF resist mask process

Towards the 65 nm technology node, Cu interconnects using a high-modulus and low-temperature porous MSQ (methyl silsesquioxane, k=2.3) process has been developed. With an advantage of a lower k value, this process is fairly compatible with the 90 nm-node technology in terms of mechanical strength of low-k film, low thermal budget to suppress SIV (stress induced void) failures, and a use of conventional ArF resist mask process. Good electrical results were obtained for 300-mm-wafer Cu dual damascene interconnects using low-pressure CMP and advanced Cu-electroplating/barrier metal processes.