Cell-plate line connecting complementary bit-line (C/sup 3/) architecture for battery-operated DRAMs

In low-voltage operating DRAMs, one of the most serious problems is how to maintain sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. An array architecture called the cell-plate line connecting complementary bit-line (C/sup 3/) architecture, which realizes a large signal voltage on the bit-line pair and low soft error rate (SER) without degrading the reliability of the memory cell capacitor dielectric film, is proposed. This architecture requires no unique process technology and no additional chip area. With the test device using the 16-Mb DRAM process, a 130-mV signal voltage is observed at 1.5-V power supply with 1.6- mu m*3.2- mu m cell size. This architecture should open the path for the future battery-backup and/or battery-operated high-density DRAMs.<
>