Fixed-point implementation of VBLAST HSDPA services

Suitable techniques for high-speed downlink packet access (HSDPA) services, using wideband code division multiple access (WCDMA), are currently being considered by the third generation partnership project (3GPP). One of the systems currently under consideration is a space-time coding (STC) architecture using the vertical-bell-labs-layered-space-time (V-BLAST) system on the downlink-shared channel (DSCH), which will allow simultaneous transmissions over multiple channels destined for a single user. Although link level results for flat fading channels indicate significant performance advantages over the conventional single antenna systems, it is less successful for frequency-selective fading. Corresponding methods of design implementation are also being developed using techniques such as system-on-a-chip (SoC), digital signal processors (DSPs), and field program gate arrays (FPGA). In this paper, we present a performance comparison for both fixed and floating point DSP implementations for the proposed V-BLAST system.