MC simulation of strained Si/SiGe devices

Transport in strained Si N- and PMOSFETs with gate lengths from 250 to 50 nm is investigated by full-band MC (Monte Carlo) device simulation. Performance improvement by strain is found for both device types, and even for the shortest gate length the on-current is enhanced by about 30% compared to the unstrained case. Thus, these simulations predict that the performance advantage of strained Si MOSFETs will scale well into the deca-nanometer gate length range. This seems to be due to the reduction in scattering by strain, leading to quasi-ballistic transport and enhanced charge carrier velocities at the source side injection point of the inversion channel.