A 30000 gate ECL gate array using advanced single poly technology and four level metal interconnect

The architecture and fabrication of a 30000 emitter coupled logic (ECL) gate array featuring a 90-ps unloaded gate delay are described. Current mode logic (CML) and ECL macros can be combined on custom-defined chips to minimize power without compromising the performance. The product has a channelless ocean-of-cells architecture permitting 100% cell utilization with ECL 100 K and 10 K I/O interface. The gate array is fabricated using ASPECT-II (advanced single poly emitter coupled technology) with silicided polysilicon local interconnect and four-level metallization.<
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