Resolving register bank conflicts for a network processor

We discuss a register bank assignment problem for a popular network processor-Intel's IXP. Due to limited data paths, the network processor has a restriction that the source operands of most ALU instructions must be resident in two different banks. This results in higher register pressure and puts additional burden on the register allocator. The current vendor-provided register allocator leaves the problem to users, leading to poor compilation interface and low quality code. We present three different approaches for performing register allocation and bank assignment. Bank assignment can be performed before register allocation, can be performed after register allocation or it could be combined with the register allocation. We propose a structure called register conflict graph (RCG) to capture the dual-bank constraints. To further improve the effectiveness of the algorithm, we also propose some enabling transformations. Our results show the phase ordering of first doing register allocation and then assigning banks can reduce the number of spills with affordable costs of additional instructions.