Zygen timing model generator

A description is given of the Zygen timing model generator tool, which provides engineers with a method for producing gate-level timing models more accurately and more quickly than by using hand calculations. The problem of assigning delays through multiple delay paths ranges from a trivial to a very complex task. The complexity arises when timing paths are reconvergent, overlapping, subdivided by nonoverlapping clocks, or when the model contains simulator-specific functions for which timings cannot be easily mapped. Zygen overcomes this complexity by employing the Zycad Magnum II hardware accelerator, Intel's reference simulator, in determining valid data paths throughout the model. In addition, it employs the power of the Simplex algorithm in solving the system of linear timing equations. A description of the algorithm and capabilities of Zygen is presented with two examples of how Zygen solved the timing problem.<
>