A fully integrated 3.3-V, 325-MHz, /spl plusmn/95-ps jitter CMOS PLL

A programmable Phase-Locked Loop architecture designed as an embedded feature in an FPGA is presented. The PLL was designed based on advanced low-power high-performance circuit design techniques, with low-output jitter, low power, and able to tolerate variations in the fabrication process. The PLL is able to generate clock signals from 61 MHz-325 MHz from a low-frequency system clock, with a maximum output jitter of /spl plusmn/95 ps.