A survey on system-on-a-chip design languages

Advancement in the microelectronics era made it possible the integration of a complete yet complex system on a single chip. Over 10 million gates, integrated together and running a real-time optimized software red crossed classical design techniques. Register level will serve as an assembly language for the new design languages or so called system level languages. The problematic is to define a language that can allow the design of such a complex systems. In this paper, we explore different paradigms of state-of-the-art of the System-on-a-Chip (SoC) modeling and design. In particular, this paper presents the main proposals in defining a system level language and discusses their advantages and drawbacks.