Internode: internal node logic computational model

In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal states the gate can reach. This computational model can be used in logic-level tools and is valid for any dynamic behavioral model (delay models, power models, switching noise models, etc.). Also, we show a very efficient implementation of the model, in C language, for N-inputs SCMOS NOR/NAND gates. Finally, we demonstrate the functionality of the model showing three different examples of modeling: (a) a propagation delay model, (b) the degradation delay model (DDM), and (c) a simple power model.