High-speed normalization and rounding circuits for pipelined floating-point processors

A fast leading/trailing-zero detection circuit (LZDC/TZDC) is described, and then applied to the design of a pipelined floating-point (FLP) processor. This circuit has a total delay of 5Δ and a hardware complexity of
(m + 1)(3 \log_{2}(p) + 4)
where Δ,
m
, and
p
are the unit gate delay, subword number, and subword partition length, respectively. Applications of this circuit to both postnormalization and rounding are presented, including circuits for normalization, sticky bit generation, and increment-by-one. The LZDC/TZDC has two important features-modularity and expandability-which make it particularly well suited for VLSI implementation.