A transform coding chip set for image compression

Two application-specific integrated circuits (ASICs) were designed to perform hierarchical transformation (S-transform processor) and Lempel-Ziv entropy coding (data compressor/decompressor). The chips can be used independently or together as a transform coding chip set for image compression. The algorithms and chip architectures of the transform codec (S-transform processor) and the entropy codec (data compressor/decompressor) are described.<
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