A word-wide 1Mb ROM with error correction

A 1Mb ROM, organized as 64K×16b or 128K×8b, that uses address/data multiplexing fit into a 28-pin package, will be reported. Combining dynamic circuit techniques with a 1.5μ double-level metal CMOS process, a typical access time of 50ns has been achieved. On-chip error correction is also available by using a modified Hamming code.