Improving the yield of deep submicron CMOS processes by controlling the grain size of poly-Si gate through post deposition rapid thermal anneal

The morphology of gate poly-Si was found to be critical for achieving fully functional 4-Mb SRAM dies with 0.18-/spl mu/m complementary metal-oxide-semiconductor (CMOS) process. Although the functionality of 4-Mb SRAM had been achieved with as-deposited poly-Si gate, it is highly likely that the surface roughness of the as-deposited poly-Si is a major concern for sub-0.18-/spl mu/m technology. In this report, it is shown that the small-size grains, achieved by recrystallizing as-deposited amorphous Si via rapid thermal anneal prior to gate patterning, is very effective in reducing the number of failing bits of 4-Mb SRAM dies. The conventional deposition process for gate poly-Si can therefore be adopted for fabricating sub-0.18-/spl mu/m CMOS integrated circuits.