A 250 Mb/s 32*32 CMOS crosspoint LSI for ATM switching systems

In the CMOS cross-point LSI described, fully synchronous switching capability for fixed-length ATM cells (packets), as well as the functions of conventional cross-point switches, has been realized. Packet broadcast capability has also been achieved as the result of input-oriented bit-map routing architecture. In order to exchange 32 packet links at the broadband line speed, tristate buffers and control latches with reduced parasitic capacitors have been utilized. The 40 k transistor chip is fabricated with a 1.0- mu m double-metal-layer n-well CMOS technology. The switch matrix is 2.4*3.2 mm. The chip size, 7.4*7.4 mm, is set by the 113 signal pads and the 39 voltage supply pads. Voltage supply nodes for output buffers are completely separated from the others. 250-Mb/s operation has been verified under nominal conditions with a 176-pin PGA package. Operating from a -4.5-V supply at 160 Mb/s, the chip dissipates 1.2 W.<
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