Accumulation of product roundoff errors in modified FFT's

In this paper, expressions are derived for the mean square error in modified radix-2 FFT algorithms. To reduce the mean square error at the output of a special purpose, high-speed low-order
(n {\leq} 32)
FFT processor implemented in fixed-point arithmetic, a modified FFT architecture is considered in which an extra bit is added to the register wordlength to prevent overflow. In this way, the scaling error is avoided and only the error due to product roundoff remains, in the case of implementation with stored-product ROM multipliers. The predicted signal/noise ratios are compared with those obtained by computer simulation.