A reduced-complexity finite field ALU

Computation by homomorphic images has been shown to be a viable technique for the VLSI implementation of real and complex arithmetic. Embedding the integers or the Gaussian integers into a direct sum of Galois fields has led to finite computational structures, which are multiplier-free; multiplication is replaced with finite field logarithm addition. While this led to an efficient realization of multiplication, addition was made more difficult. The authors propose a scheme to allow both addition and multiplication with finite field logarithms that alleviates the earlier difficulties with addition and leads to a more compact hardware realization.<
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